In the manufacture of integrated circuits, high performance transistors are often built on high mobility channel regions formed of silicon germanium. One conventional process for building such transistors begins by depositing a gate stack, such as a dielectric layer and a gate electrode, on a silicon germanium layer over a silicon substrate. At least two ion implantation processes are then carried out. A first ion implantation forms lightly doped drain (LDD) implant regions that will later serve as source and drain extension regions. A second, more intense ion implantation then forms halo regions that help control short channel effects. The rest of the fabrication process builds the remaining parts of the transistor, such as spacers, source and drain regions, an interlayer dielectric, and connections to the transistor.
It has been observed that this conventional process yields a substantial number of defects in the LDD implant regions, thereby allowing a large number of defects to be present in the source and drain extension regions of the transistor. These defects are not annealed out during the subsequent thermal budget, such as during dopant activation anneals when the source and drain regions are formed. Defects in the source and drain extension regions reduce performance of the transistor, for instance, short channel effects are worse and junction leakage is high, resulting in higher I-off levels. Accordingly, a new fabrication process is needed to reduce or eliminate such defects.